Revela ISP
a complete camera ISP generated from NumPy, running on FPGA
Last verified:
What is Revela ISP?
Revela ISP is an open-source image signal processor written in NumPy that compiles to verified hardware (Verilog/FPGA). It processes raw Bayer camera data through stages like black level correction, white balance, demosaicing, color matrix, and gamma, entirely in hardware without hand-written RTL.
Revela ISP pricing
Pricing model: Freemium
Free (open source) — optional GitHub Sponsors support
Revela ISP pros
- Bit-exact verification: Python model automatically generates Verilog and verifies hardware matches exactly
- No hand-written Verilog anywhere — all RTL auto-generated from NumPy expressions, reducing verification burden
- Compiler automatically places pipeline registers based on timing constraints, eliminating manual placement
- Modular, reusable blocks designed as building blocks for ASICs using open RISC-V cores
Revela ISP cons
- Early-stage project with limited algorithm coverage; patents expiring gradually means more blocks available over time
- Demo limited to specific hardware (PYNQ-Z2 FPGA board + Raspberry Pi camera, 1920×1080 10-bit output)
- No commercial support or professional licensing mentioned; community-driven development via GitHub Sponsors
Frequently asked questions about Revela ISP
How is verification handled?
The NumPy model is the specification from which Verilog is generated. Generated hardware is checked bit-exact against the model before release; mismatches cause generation to fail.
Can I use this in production hardware?
Yes — Revela is designed as a building block for ASICs. The demo runs on FPGA (PYNQ-Z2), but components can be integrated into full chips with open RISC-V cores.
Is it really free?
Yes, all components are open source on GitHub. Installation is via pip (revela, np2hw, bayerlink). The creator accepts optional support via GitHub Sponsors.