XCENA
Provides CXL computational memory devices to expand data center capacity and reduce processing latency
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What is XCENA?
XCENA is a fabless semiconductor startup that provides intelligent memory solutions based on Compute Express Link (CXL) technology. The company's flagship product is the MX1, a CXL Computational Memory device that merges high-capacity pooled DDR5 memory with near-data processing (NDP) cores containing thousands of proprietary RISC-V processing units. This architecture redefines data center infrastructure for the AI era by expanding memory beyond traditional CPU limits and executing computation where data resides, significantly reducing latency, energy consumption, and total cost of ownership.
The MX1 supports CXL 3.0 with memory expansion up to 1TB using four channels of 256GB DDR5 DIMMs without increasing CPU memory channels, and provides bandwidth expansion up to 128GB/s through PCIe Gen6 interface. XCENA also provides a full-stack SDK with multi-level APIs, emulation/simulation tools, and drivers for multiple operating systems to facilitate seamless integration with applications and workflows. The software stack offers high-level runtime APIs for easy adoption without major architectural changes, plus low-level device APIs for fine-tuned optimization.
XCENA's technology is specifically designed for fields requiring large-scale data processing including AI/LLM inference (KV cache offloading), RAG systems with vector databases, scale-out databases (Spark, Databricks, Snowflake), graph databases, DNA analytics, and big data analysis. The FPGA prototype demonstrated 46% reduction in query processing time compared to server CPUs in database acceleration, with potential reductions up to 95% in ASIC based on TPC-H benchmarks.
The company was founded in 2022 by semiconductor veterans from Samsung and SK hynix, raised $135M in Series B funding in May 2026 at a $570M valuation (total funding $185M), and is preparing to manufacture its inaugural ASIC chip scheduled for release in the first half of 2027. XCENA has established offices in South Korea and Silicon Valley, California, targeting hyperscalers, telcos, database companies, and research institutions.
XCENA pricing
Pricing model: Freemium
XCENA does not publish public pricing on its website. As an enterprise semiconductor company targeting hyperscalers, telcos, database companies, and research institutions, pricing is custom and negotiated directly with the company. The MX1 computational memory device is sold as enterprise hardware with working samples available to select partners beginning October 2025. XCENA raised $135M in Series B funding at a $570M valuation in May 2026, bringing total funding to $185M. No free tier is available as this is enterprise-grade semiconductor hardware.
XCENA pros
- Supports CXL 3.0 standard for open, interoperable memory expansion
- Memory expansion up to 1TB without additional CPU memory channels
- Bandwidth expansion up to 128GB/s via PCIe Gen6 interface
- Thousands of proprietary RISC-V cores for near-data processing
- 46% faster query processing vs server CPUs (FPGA prototype)
- Up to 95% performance improvement potential with ASIC (TPC-H benchmarks)
- Reduces latency by executing computation where data resides
- Significantly lowers energy consumption and TCO
- Full-stack SDK with multi-level APIs for easy integration
- High-level runtime APIs require no major architectural changes
- Low-level device APIs for fine-tuned data movement control
- Supports major operating systems with drivers
- Includes emulation/simulation tools for development
- Double die Chipkill Correction for strong RAS features
- Multi-bit/multi-die DRAM ECC prevents critical system errors
- SSD RAID functionality for enhanced reliability
- Built on Samsung Foundry's advanced 4nm process technology
- Ideal for LLM KV cache offloading and RAG systems
- Accelerates vector databases, graph databases, and scale-out analytics
- Enables KV reuse across workers with zero-copy access
XCENA cons
- ASIC chip not yet released (scheduled for first half of 2027)
- Currently only FPGA prototypes available for evaluation
- Working samples only accessible to select partners starting October 2025
- Requires CXL 3.0-compatible infrastructure and servers
- Enterprise-only product with no consumer availability
- Pricing details not publicly disclosed (custom enterprise pricing)
- Limited to hyperscalers, telcos, and research institutions
- New company with limited deployment history compared to incumbents
- Requires integration expertise for optimal workload acceleration
- MX1S variant not available until 2026
Frequently asked questions about XCENA
What is XCENA's MX1 computational memory?
The MX1 is XCENA's flagship CXL Computational Memory device that combines high-capacity pooled DDR5 memory (up to 1TB) with thousands of proprietary RISC-V cores for near-data processing (NDP). It supports CXL 3.0 and PCIe Gen6, enabling memory expansion without additional CPU memory channels while executing computation where data resides to reduce latency and TCO.
What is near-data processing (NDP) and how does it help?
Near-data processing is a technology where XCENA's multi-core processor performs parallel offloading tasks directly near the data instead of moving data to the CPU. This minimizes latency from data movement across interfaces, reduces unnecessary data replication, and significantly improves processing speed and efficiency, potentially reducing TCO for large-scale data processing applications.
What performance improvements does XCENA deliver?
XCENA's FPGA prototype demonstrated a 46% reduction in query processing time compared to server CPUs in database acceleration based on TPC-H benchmarks. With the ASIC implementation, potential reductions up to 95% are achievable. The technology also stabilizes latency and significantly lowers cost per token in LLM inference through KV cache reuse.
What applications is XCENA best suited for?
XCENA is optimized for AI/LLM inference (especially KV cache offloading), RAG systems with vector databases, scale-out databases like Spark/Databricks/Snowflake, graph databases, DNA analytics, and big data analysis. These are fields requiring large-scale data processing where memory bottlenecks are significant.
What SDK and software support does XCENA provide?
XCENA provides a full-stack SDK with multi-level APIs, emulation/simulation tools, and drivers for multiple operating systems. The software stack includes high-level runtime APIs that enable applications to leverage CXL computational memory without major architectural changes, plus low-level device APIs for fine-tuning data movement and compute execution for maximum efficiency.
What are the RAS (Reliability, Availability, Serviceability) features?
XCENA's Computational Memory supports double die Chipkill Correction, multi-bit/multi-die DRAM ECC (Error Correction Code) to prevent critical system errors, and SSD RAID functionality for enhanced reliability. These features prevent errors caused by various issues in mission-critical data center environments.
When will the MX1 be available for purchase?
XCENA is preparing to manufacture its inaugural ASIC chip scheduled for release in the first half of 2027. Working samples will be accessible to select partners beginning in October 2025. The MX1P is anticipated to launch later in 2025, while the MX1S variant with dual PCIe Gen6 x8 links is slated for 2026.
How does XCENA help with LLM inference and KV cache?
In LLM inference, KV cache size grows rapidly with context length and batch size, creating a performance bottleneck. XCENA's CXL memory introduces a shared memory pool that expands capacity beyond GPU memory, enabling KV reuse across workers. With CXL's load/store semantics, KV data can be accessed with zero-copy, reducing recomputation, stabilizing latency, and lowering cost per token.
What is XCENA's funding and company background?
XCENA was founded in 2022 by semiconductor veterans from Samsung and SK hynix. The company raised $135M in Series B funding in May 2026 at a $570M valuation, bringing total funding to $185M. The round was co-led by Altinum and IMM Investment. XCENA has offices in South Korea (Seongnam-si) and Silicon Valley, California, with 90 employees.
What CXL specifications does XCENA support?
XCENA's Computational Memory supports CXL 3.0, Type 3 device with Back Invalidation, supporting both CXL.io and CXL.mem protocols. It includes XCENA's own CXL controller and can expand up to TB-scale DDR5 memory. The MX1 also supports CXL 3.2, with the MX1S variant featuring dual PCIe Gen6 x8 links planned for 2026.